Low Power Efficient Adder Design for VLSI

This book proposes an energy efficient approximate adder that provides low power high performance addition without severe quality degradation. The proposed adder introduces area efficient approximate logic that is used to adder the least significant bits of the adder. The effectiveness of the adder is analyzed over the well known accurate and approximate adders by implementing on Tanner and MATLAB. The prime challenge in the modern VLSI technology is the energy efficiency due to increased functionality on the single chip. The energy efficiency can be achieved through designing circuit imprecisely for a specific domain of applications known as error tolerant applications. This paper proposes an energy efficient adder architecture that achieves tremendous improvement in both the power and speed performance.The efficacy of the proposed adder is evaluated by implementing the proposed and existing adder architecture on MATLAB to evaluate error metrics and on Tanner to evaluate design metrics. Simulation results show that the proposed adder significantly reduces power, area and delay simultaneously at small loss in accuracy.